module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a,c1,d1);
and(w3,a,b,d1);
and(w4,a,b1,c,d);
and(w5,a1,b1,c,d1);
or(e,w1,w2,w3,w4,w5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule